To reduce loads to a CPU and time till starting of DMA transfer by setting the number of transfers without using the CPU.

This DMA transfer device comprises a DMA transfer number register 131 and reads transfer number data from an FIFO 120 connected via a bus 140 and stores the data in the DMA transfer number register 131. Data are transferred from the FIFO 120 till the number of transfers indicated by the transfer number data stored in the DMA transfer number register 131 becomes to 0. The transfer number is reduced by one every time the data is transferred from the FIFO 120. Since the transfer number data can be read into the DMA before starting of DMA transfer and returning the process to the CPU is not needed at starting of the DMA transfer, a cycle can be shortened before starting of the transfer and the loads to the CPU can be reduced compared to conventional DMA.