PURPOSE: To improve the throughput of a CPU part by providing a bus right arbitrating part, separating the data bus of the CPU part from an IO part bus under necessary conditions and executing a bus action by means of the CPU part.

CONSTITUTION: When a bus request is executed from a CPU part 2 while a data bus 13 of the CPU part 2 is in an unused period in a period when a DMA transfer is executed between an IO part 4 and a memory part 5 by a DMA control part 3, a switching signal is outputted from the switching part of a bus right arbitrating part 17, and it is impressed to a bidirectional buffer 18. Then, the bus 13 and a data bus 19 of the IO part 4 is cut off and separated by a buffer 18, and the CPU part 2 can execute the bus action. As a result, without giving a trouble to the DMA control, the throughput of the CPU part can be increased.