Title:
DOT INTERFERENCE REDUCTION CIRCUIT
Document Type and Number:
Japanese Patent JPS6473888
Kind Code:
A
Abstract:
PURPOSE:To reduce dot interference without deteriorating picture quality by inserting 3.58MHz detection circuits to a luminance signal line and a chrominance signal line separated by a comb-line filter, respectively, and operating a notch filter only when 3.58MHz components exist in both a luminance signal and a chrominance signal. CONSTITUTION:When the comb-line filter 1 is operated on a video signal without having vertical correlation, the 3.58MHz components appear in both a chrominance signal and a luminance signal components, and they are detected at detection circuits 5 and 6. Detecting signals are outputted from the detection circuits 5 and 6, and are added on a transistor 8 via an AND gate 7, and the transistor 6 is energized, thereby, the notch filter 2 is operated. In such a way, it is possible to reduce the dot interference without missing the 3.58MHz component in the luminance signal, and to improve the picture quality remarkably. Also, since an integration circuit 53 and a peak detection circuit 54 are used in the detection circuit for the 3.58MHz component, it is possible to always detect the 3.58MHz component with a level more than a prescribed level.
Inventors:
SAKAOKA MASAMI
Application Number:
JP23018087A
Publication Date:
March 20, 1989
Filing Date:
September 14, 1987
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H04N9/78; H04N9/64; (IPC1-7): H04N9/64; H04N9/78