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Title:
DOUBLE DIFFUSED INSULATED GATE TYPE FET
Document Type and Number:
Japanese Patent JPS6027170
Kind Code:
A
Abstract:

PURPOSE: To prevent the step cut of wiring at the part of contact by a method wherein polycrystalline Si is buried at the bottom surface of an aperture of the source contact, etc.

CONSTITUTION: Source regions 4 and 5 and a channel base region 42 are formed in the surface of a low concentration Si layer 2. The region 42 consists of only a low concentration P layer. A polycrystalline Si layer 41 of low resistance is buried in the aperture of an interlayer insulation film 8. The layer 41 is N type above the regions 4 and 5 and P type above between them. The layer 41 is buried at the entire part in the aperture, the upper surface of the film 8 being even with that of the layer 41 without any stepwise difference, and a source electrode wiring 43 and a gate electrode wiring 44 being then formed thereon.


Inventors:
NAKAYAMA YOSHIHITO
TANABE HIROHITO
OOHATA TAMOTSU
MIWA YUKINOBU
SUZUKI KAZUAKI
Application Number:
JP13414383A
Publication Date:
February 12, 1985
Filing Date:
July 22, 1983
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
H01L29/45; H01L29/78; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Takehiko Suzue



 
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