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Title:
DOUBLE TOTALIZATION PREVENTING DEVICE AT SERVICE INTERRUPTION
Document Type and Number:
Japanese Patent JPS56111926
Kind Code:
A
Abstract:

PURPOSE: To avoid a double totalization during a service interruption, by installing an F.F for service interruption detection flag to the arithmetic processor having no interruption process function and independently from a nonvolatile memory.

CONSTITUTION: The nonvolatile memory 1 includes the arithmetic (total data) area 2, auxiliary area 3, process memory counter 4, number data area 5, unit price data area 6 and process contents memory flag 7 respectively. In addition, the service interruption detection flag F.F8 is provided independently from the memory 1. Thus the service interruption detector circuit 10 discontinues the process of the arithmetic processor 9 having no interruption process function in case the service is interrupted while the processor 9 is carrying out a total process. At the same time, the nonvolatile F.F8 is set. When the service interruption is recovred, the processor 9 reads the contents of the counter 4 by the settig of the F.F8 to decide that the process is finished up to the item (i). Thus an arithmetic process is given to the totalization of the item (i+1) with use of the data of the item (i) within the memory 1.


Inventors:
NORIKANE NAOKI
Application Number:
JP1464180A
Publication Date:
September 04, 1981
Filing Date:
February 07, 1980
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F7/00; G06F1/30; G06F9/48; G06F11/00; (IPC1-7): G06F1/00; G06F7/00; G06F11/00



 
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