Title:
DRAM CELL INCLUDING SUBMERGED ANNULAR TRANSISTOR AND COUPLED TRENCH CAPACITOR AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH05102421
Kind Code:
A
Abstract:
PURPOSE: To improve cell density and reliability and to manufacture a DRAM cell easily, by forming the bit line of a second-type dopant on a substrate containing a first-type dopant and providing a gate oxide layer and a polycrystalline silicon gate on a side wall and a trench filled with polycrystalline silicon on a bottom. CONSTITUTION: A second-type dopant that is opposite to a first type is introduced to a semiconductor substrate containing a first-type dopant and a narrow region of a stripe 32 that has already been doped is formed on the surface of the semiconductor substrate closely, and a recess 36 extended through a stripe 32 is formed. Then, doping is introduced to the bottom of the recess 36, an insulation layer 42 is formed on the wall and the bottom of the recess 36, and a polycrystalline layer is formed on the wall of the recess 36. Then, only the layer of the bottom of the recess 36 is eliminated, the polycrystalline layer is partially oxidized and the thick insulation layer 42 is formed on it, a trench 48 is formed at the center part of the recess 36, and the surface is subjected to lining by the insulation layer 42. Then, the trench 48 is filled with polycrystalline silicon 52.
Inventors:
FUANNCHIN CHIYAO
Application Number:
JP3485592A
Publication Date:
April 23, 1993
Filing Date:
February 21, 1992
Export Citation:
Assignee:
IND TECH RES INST
International Classes:
H01L27/04; H01L21/822; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/04; H01L27/108
Attorney, Agent or Firm:
Kyozo Yuasa (6 people outside)