DRAM CONTROLLER

Japanese Patent JP3768565

B2

PROBLEM TO BE SOLVED: To provide the DRAM controller in which a control circuit is integrated. SOLUTION: A 1st reset signal is active till a voltage of a main power supply is a 1st threshold voltage or below or till a prescribed time elapses after the voltage exceeds the threshold level. A 2nd reset signal is active till a voltage of a monitor signal is a 2nd threshold voltage or below or till a prescribed time elapses after the voltage exceeds the threshold level. Power is supplied from the main power supply or a standby power supply to DRAMs 10, 11. The standby power supply is charged by the main power supply. A DRAM control means 8 is driven by the main power supply and transits the DRAMs 10, 11 to a backup state when the 1st reset signal is active and a monitor voltage output is changed to be the 2nd threshold level or below. When the 1st reset signal is inactive, the monitor voltage output is set to a voltage in excess of the 2nd threshold level to restore the DRAMs 10, 11 from the backup state. The CPU 7 is driven by the main power supply and reset by the 2nd reset signal.