PURPOSE: To provide the DRAM of an FIFO type which can exceedingly save electric power consumption during stand-by and is adequate for portable type apparatus, such as portable telephone sets, and small-sized apparatus, such as IC cards.

CONSTITUTION: A refresh circuit having a refresh controller 13, a refresh timer 14 and a refresh address pointer 10, etc., is provided. A clock signal CK' is inputted thereto in the state of disabling a write enable signal WE and an output enable signal OE. The refresh controller 13 emits a control signal to the refresh address pointer 10 and forms the address signal for causing the refresh address pointer 10 to increment the addresses of the memory array 1 by one each at every time the clock signal CK falls from a '1' level to a '0' level within a certain specified period of time. The refresh operation of the data stored and held in the memory cells of the memory array 1 is executed according to the address signal. The period of the clock signal CK is made as long as possible in order to reduce the electric power consumption during the stand-by.