PURPOSE: To reduce a chip size and to enable high-speed access and high-speed cycle by executing write transfer from a static memory cell to a dynamic memory cell while stopping operation in one of both P and N channel sense amplifiers at least.

CONSTITUTION: The DRAM with built in SRAM consist of a DRAM block arranging dynamic memory cells MBnear and MB far at the intersections of word lines and bit lines to be arranged as a matrix, a SRAM block arranging static memory cells SM0, SM1... for every paired bit lines and a gate inserted to the bit line and to separate the DRAM block from the SRAM block. The static memory cell is defined as a data register and the write transfer from the static memory cell to the dynamic memory cell is executed while stopping the operation of one of the both P and N channel sense amplifiers at least. Thus, since the SRAM is used as the data register, the chip size is reduced and the high-speed access and the high-speed cycle can be executed.