To provide a driver circuit in which the length of a dead time can be measured accurately.

In the driver circuit 100, two output transistors MH1 and ML1 are provided in series between the first power voltage Vdd and a grounding potential. In usual operation, a dead time generating circuit 30 gives a delay for a dead time, so that two output transistors MH1 and ML1 may not be switched on at the same time, to drive signals SH1' and SL1' for controlling the ON-OFF of the two output transistors MH1 and ML1, and outputs them to the two output transistors MH1 and ML1, and in testing the length of the delay for a dead time, it gives a delay for test, which has a specified relation with the delay for a dead time and is longer than the delay for a dead time, to the drive signals and outputs them to the transistors.