PURPOSE: To evade the setting of a velocity saturated state and to obtain satisfactory frequency characteristic by dividing a clock buffer which drives a charge transfer device at need, and furthermore, dividing a clock logic circuit which drives the buffer.

CONSTITUTION: A fundamental clock for the driving of the charge device(CCD) 2 is inputted from a clock input terminal 8 to a second clock logic circuit 7, and waveform shaping is applied to the output of the circuit by using (n) first clock logic 6-1 to 6-2, and a required timing is generated, and it is inputted to (n) clock buffer circuits 5-1 to 5-n, and the charge transfer of the CCD 2 is performed by using clocks supplied from the (n) clock buffer circuits 5-1 to 5-n. Meanwhile, an input signal is converted to a charge signal at the input part of the CCD 2, and is transferred to the output part of the CCD 2, and is converted to an electrical signal, and is processed by a signal processing circuit 3, then, it is outputted to an output terminal 4. Thereby, it is possible to evade the setting of the velocity saturated state and to obtain the satisfactory frequency characteristic.