Title:
DRIVING-FREE PULSE GENERATION CIRCUIT
Document Type and Number:
Japanese Patent JPS59139088
Kind Code:
A
Abstract:
A variable format CRT display is driven by a transistor 10 which is turned-off by a synchronising pulse 20 and is turned on when the coil current generated by a diode and capacitor circuit 44 reaches a settable threshold 54. Drift compensation is exercised by a delay mechanism fixed by the synchronising pulse, which sets a latch 22, quenching transistor 25 and allowing capacitor 26 to charge through a variable resistance 46. When the ramp voltage 24 attains the voltage of a second capacitor 27, comparator 18 generates a pulse 30 setting latch 12 and turning off transistor 10. The flyback current 43a is clipped to a pulse 43b which fires transistor 40 to enable a current minor 34, 45 to charge capacitor 27 until the ramp voltage reaches a reference value 29 whereat capacitor 27 discharges and capacitor 26 is discharged. If discharge is not centred on pulse 43b, the charged state of capacitor 27 will vary to tend to maintain centring. Variables 32, 36 and 54 exercise gross control.
Inventors:
POORU UIRIAMU BONDO
JIEEMUZU DONARUDO ROTSUKUROOA
JIEEMUZU DONARUDO ROTSUKUROOA
Application Number:
JP19448983A
Publication Date:
August 09, 1984
Filing Date:
October 19, 1983
Export Citation:
Assignee:
IBM
International Classes:
G09G1/16; G09G1/04; G09G5/12; G09G5/18; H03K4/64; H04N3/24; (IPC1-7): G09G1/04
Attorney, Agent or Firm:
Jiro Yamamoto