Title:
INPUT TUNING CIRCUIT
Document Type and Number:
Japanese Patent JP3212711
Kind Code:
B2
Abstract:
PURPOSE: To provide the input tuning circuit for reducing image interference over an entire band and for securing a sufficient reception range by varying a frequency of an image trap in interlocking with a tuning voltage.
CONSTITUTION: A resonance circuit X comprising an image trap coil L5, a tuning capacitor C4, a coupling capacitor C5, a DC component blocking capacitor C6, an image trap capacitor C7, and a tuning correction diode D4 is formed. Since the resonance circuit X includes the varactor diode D4 and its resonance frequency is variable by the tuning voltage, the image trap is formed by making the resonance frequency to coincide with the image frequency. The resonance frequency of image trap is optionally set without giving much effect on the resonance frequency variable range of the tuning circuit by connecting the image trap capacitor C7 to the circuit X.
Inventors:
Kazuhiko Goto
Application Number:
JP24742292A
Publication Date:
September 25, 2001
Filing Date:
September 17, 1992
Export Citation:
Assignee:
Sharp Corporation
International Classes:
H03J5/24; H04B1/18; (IPC1-7): H03J5/24; H04B1/18
Domestic Patent References:
| JP352323A | ||||
| JP2250422A | ||||
| JP697779A | ||||
| JP2241230A | ||||
| JP61128843U | ||||
| JP241519U | ||||
| JP61184318U |
Attorney, Agent or Firm:
Shizuo Sano