Title:
デュアルエッジM/Nカウンタ
Document Type and Number:
Japanese Patent JP4927301
Kind Code:
B2
Abstract:
A counter for synthesizing clock signals with minimal jitter. The inventive counter has a first counter stage; a look-ahead circuit input connected to said first counter stage; and a selection circuit for choosing between an output of said first counter stage and an output of said look-ahead circuit as an output of said counter. In the specific embodiment, the first counter stage is adapted to receive a first clock signal having a frequency of N cycles per second and output a second clock signal having a frequency of M cycles per second. The first counter stage includes an accumulator having a rollover point at which an instantaneous count thereof exceeds the value of N-M. The look-ahead circuit determines for a present clock cycle the rollover point for a preceding clock cycle. The look-ahead circuit is a second counter stage adapted to ascertain whether the rising edge or the trailing edge of the second clock signal is closer to the rollover point and output an indication with respect thereto.
Inventors:
Halter, Stephen Jay
Application Number:
JP2002527053A
Publication Date:
May 09, 2012
Filing Date:
September 12, 2001
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
H03K23/64; H03K23/68
Domestic Patent References:
| JPH114160A | 1999-01-06 | |||
| JPH04227330A | 1992-08-17 | |||
| JPH02148913A | 1990-06-07 | |||
| JPH0296429A | 1990-04-09 | |||
| JPH03283029A | 1991-12-13 |
Attorney, Agent or Firm:
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Makoto Nakamura
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto