Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
DUAL EDGE PROGRAMMABLE DELAY UNIT
Document Type and Number:
Japanese Patent JP2005168029
Kind Code:
A
Abstract:

To provide a delay unit capable of shortening a delay time to a picoseconds (ps) range.

A method and a device program a dual edge programmable delay unit that responds to an input signal with a a rise time and a fall time, includes a buffer which receives the input signal and provides an output signal with programmed variable delays between the rise and fall times of the output signal. Programmable control sources (PCS) provide separate control inputs to a buffer. The FTPCS charges a capacitor in the buffer when the input signal changes from high to low to adjust a time delay before the fall of the buffer output signal. The RTPCS discharges the capacitor in the buffer when the input signal changes from low to high to adjust the time delay before the rise of the buffer output signal.


Inventors:
FENG KAI D
WU HONGFEI
Application Number:
JP2004349506A
Publication Date:
June 23, 2005
Filing Date:
December 02, 2004
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
IBM
International Classes:
G01R1/00; H03H11/26; H03K5/06; H03K5/13; H03K5/14; H03K5/1532; H03K17/693; H03K19/0948; H03K19/173; H03K5/00; (IPC1-7): H03K5/13; H03K5/1532; H03K19/0948; H03K19/173
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno