Title:
DUAL GATE MOS THYRISTOR
Document Type and Number:
Japanese Patent JP3161092
Kind Code:
B2
Abstract:
PURPOSE: To eliminate parasitic effect preventing thyristor operation of an element itself by achieving low-resistance connection of the drain region of MOSFET to a first conductive base layer and that of the source region to a second conductive type emitter layer in thyristor structure.
CONSTITUTION: A MOSFET is formed by 501 on a silicon substrate in pnpn structure consisting of a P+ layer 1, an n+ layer 2, an n layer 3, a p region 4, and an n+ region 5. Namely, an impurity is doped to a polycrystalline silicon layer deposited on the n- layer 3 via an oxide film 9, thus forming a p+ drain region 15 and a p+ source region 16 with a resistivity which is approximately several Ωcm while holding a p-type channel formation region 14 with a resistivity of approximately 0.1Ωcm. Then, a second gate electrode 18 consisting of a polycrystalline silicon with a resistivity of approximately several Ωcm via a gate oxide film 17 on the surface of the p region 14. The MOSFET is short- circuited, thus shirting from thyristor operation to IGBT operation.
Inventors:
Yasukazu Seki
Application Number:
JP29545292A
Publication Date:
April 25, 2001
Filing Date:
November 05, 1992
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H01L29/74; H01L21/336; H01L27/04; H01L29/739; H01L29/749; H01L29/78; (IPC1-7): H01L29/749
Domestic Patent References:
| JP5335554A | ||||
| JP5326936A | ||||
| JP5315619A | ||||
| JP5235363A | ||||
| JP418763A | ||||
| JP3148872A | ||||
| JP3145163A | ||||
| JP3136371A | ||||
| JP1181571A | ||||
| JP63288064A | ||||
| JP5778225A |
Other References:
【文献】平成4年電気学会全国大会講演論文集,No.5,p.5.7(1992)[デュアルゲートMOSゲートサイリスタ[DUGMOT]」
Attorney, Agent or Firm:
Masaharu Shinobe