Dual gated mode III-V fellows compound transistor - International Rectifier Corporation

Title:

Dual gated mode III-V fellows compound transistor

Document Type and Number:

Japanese Patent JP6049674

Kind Code:

B2

Abstract:

A group III-V merged cascode transistor (200) includes a group III-V body (220) disposed over a substrate (210) and configured to produce a two-dimensional electron gas (2DEG). The group III-V body includes a group III-V barrier layer (224) situated over a group III-V channel layer (216), and a source electrode (240) and a drain electrode (230). The group III-V merged cascode transistor also includes an enable gate (260) disposed in a recess (226) extending through the group III-V barrier layer, and an operational gate (270) disposed over the group III-V barrier layer, the operational gate not being in physical contact with the enable gate.

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Inventors:

Michael A. Briar

Application Number:

JP2014235392A

Publication Date:

December 21, 2016

Filing Date:

November 20, 2014

Export Citation:

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Assignee:

International Rectifier Corporation

International Classes:

H01L21/337; H01L21/336; H01L21/338; H01L21/8232; H01L21/8234; H01L21/8236; H01L27/06; H01L27/088; H01L27/095; H01L29/06; H01L29/41; H01L29/778; H01L29/78; H01L29/808; H01L29/812

Domestic Patent References:

JP2011228398A
JP2011243978A
JP2013069785A

Attorney, Agent or Firm:

Einzel Felix-Reinhard
Takuya Kuno

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