Title:
DUAL-MODE TRANSISTOR DEVICE AND METHOD FOR OPERATING THE SAME
Document Type and Number:
Japanese Patent JP2014239202
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a memory structures that supports more efficient operation and low leakage.SOLUTION: A dual-mode transistor structure comprises a semiconductor body 10. The semiconductor body of the device includes a channel region 13, a p-type terminal region 14 (operable as a source or drain) adjacent a first side of the channel region, and an n-type terminal region 15 (operable as a source or drain) adjacent a second side of the channel region. A gate insulator 12 is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate 16A is disposed on a first side of the gate, and a second assist gate 16B is disposed on a second side of the gate. Optionally, a back gate 18 can be included beneath the channel region. Biasing the assist gates can be used to select an n-channel mode or a p-channel mode in a single device.
Inventors:
LUE HANG-TING
CHEN WEI-CHEN
CHEN WEI-CHEN
Application Number:
JP2014013836A
Publication Date:
December 18, 2014
Filing Date:
January 28, 2014
Export Citation:
Assignee:
MICRONICS INT CO LTD
International Classes:
H01L29/786; H01L21/336; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2007134721A | 2007-05-31 | |||
| JPH0410659A | 1992-01-14 | |||
| JPH05167097A | 1993-07-02 | |||
| JP2007134721A | 2007-05-31 | |||
| JPH0410659A | 1992-01-14 | |||
| JPH05167097A | 1993-07-02 |
Attorney, Agent or Firm:
Patent business corporation far international patent firm
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