Title:
非常に高い周波数で動作するデュアル・モジューラス・プリスケーラ回路
Document Type and Number:
Japanese Patent JP5090324
Kind Code:
B2
Abstract:
The circuit (1) has two NAND gates (15, 16) arranged in negative feedback between two dynamic D-type flip flops (12, 13) which are clocked by an input clock signal (CK) to supply a divided output signal (OUT) whose frequency is matched with an input clock signal frequency divided by a factor equal to 2 or 3 as a function of a division mode selection signal (divb) applied to an input of one of the NAND gates. An output of one flip flop is connected to an input of the other flip flop, where one of the flip flops is formed of three active branches to provide only one inverted output signal.
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Inventors:
Arnaud Casagrande
Carlos Velasquez
Jean-Luc Arend
Carlos Velasquez
Jean-Luc Arend
Application Number:
JP2008315392A
Publication Date:
December 05, 2012
Filing Date:
December 11, 2008
Export Citation:
Assignee:
The Swatch Group Research and Development Limited
International Classes:
H03K23/66; H03K3/037; H03K3/356; H03K19/096; H03K21/10; H03K23/52
Domestic Patent References:
| JP1316023A | ||||
| JP2013127A | ||||
| JP2048823A |
Attorney, Agent or Firm:
Masaki Yamakawa
Shigeki Yamakawa
Shigeki Yamakawa