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Title:
DUAL MODULUS PRESCALER
Document Type and Number:
Japanese Patent JP2010178120
Kind Code:
A
Abstract:

To increase a setup margin and to perform an operation at a higher speed.

The dual modulus prescaler includes 9 pieces of flip-flops U12, U4-U11 cascade-connected in a ring shape and a NAND gate U3. The flip-flops U12, U4-U11 are arrayed in the order from the initial stage to the final stage, and each comprises the flip-flop of a master/slave system. To the master latch of the flip-flop U12, a NOR gate G1 to which a frequency dividing ratio switching terminal T-PS is connected is incorporated.


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Inventors:
Takahashi, Hiroshi
Application Number:
JP2009000019285
Publication Date:
August 12, 2010
Filing Date:
January 30, 2009
Export Citation:
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Assignee:
ICOM INC
International Classes:
H03K23/54; H03K3/356; H03K23/64; H03K23/66
Domestic Patent References:
JPH01303926A
JPS6348014A
JPS61144121A
JPS62198726U
JPH04162817A
JPS60145721A
Attorney, Agent or Firm:
小谷 悦司
小谷 昌崇
西谷 浩治



 
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