Title:
DUAL MODULUS PRESCALER
Document Type and Number:
Japanese Patent JP2010178120
Kind Code:
A
Abstract:
To increase a setup margin and to perform an operation at a higher speed.
The dual modulus prescaler includes 9 pieces of flip-flops U12, U4-U11 cascade-connected in a ring shape and a NAND gate U3. The flip-flops U12, U4-U11 are arrayed in the order from the initial stage to the final stage, and each comprises the flip-flop of a master/slave system. To the master latch of the flip-flop U12, a NOR gate G1 to which a frequency dividing ratio switching terminal T-PS is connected is incorporated.
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Inventors:
TAKAHASHI HIROSHI
Application Number:
JP2009019285A
Publication Date:
August 12, 2010
Filing Date:
January 30, 2009
Export Citation:
Assignee:
ICOM INC
International Classes:
H03K23/54; H03K3/356; H03K23/64; H03K23/66
Domestic Patent References:
| JPH01303926A | 1989-12-07 | |||
| JPS6348014A | 1988-02-29 | |||
| JPS61144121A | 1986-07-01 | |||
| JPS62198726U | 1987-12-17 | |||
| JPH04162817A | 1992-06-08 | |||
| JPS60145721A | 1985-08-01 |
Attorney, Agent or Firm:
Etsushi Kotani
Masataka Otani
Koji Nishitani
Masataka Otani
Koji Nishitani