Title:
デュアルモジュラスプリスケーラ
Document Type and Number:
Japanese Patent JP5223704
Kind Code:
B2
Abstract:
To increase a setup margin and to perform an operation at a higher speed.
The dual modulus prescaler includes 9 pieces of flip-flops U12, U4-U11 cascade-connected in a ring shape and a NAND gate U3. The flip-flops U12, U4-U11 are arrayed in the order from the initial stage to the final stage, and each comprises the flip-flop of a master/slave system. To the master latch of the flip-flop U12, a NOR gate G1 to which a frequency dividing ratio switching terminal T-PS is connected is incorporated.
COPYRIGHT: (C)2010,JPO&INPIT
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Inventors:
Hiroshi Takahashi
Application Number:
JP2009019285A
Publication Date:
June 26, 2013
Filing Date:
January 30, 2009
Export Citation:
Assignee:
Icom Co., Ltd.
International Classes:
H03K23/54; H03K3/356; H03K23/64; H03K23/66
Domestic Patent References:
| JP1303926A | ||||
| JP63048014A | ||||
| JP61144121A | ||||
| JP62198726U | ||||
| JP4162817A | ||||
| JP60145721A |
Attorney, Agent or Firm:
Etsushi Kotani
Masataka Otani
Koji Nishitani
Masataka Otani
Koji Nishitani