PURPOSE: To prevent a write operation and a read operation from simultaneously being executed by once holding a data signal in a write data holding means and holding the data signal of a contention memory cell in a read data holding means.

CONSTITUTION: Signals RDb and RDENb are asserted in response to the fall of the signal RDb for reading through an access port B. At the same time, the state of the other access port A is detected by an access contention detection circuit 8a. When the other access port A requests writing into the same memory cell, the access contention detection circuit 8a outputs a contention detection signal SELb. In such a case, a switching circuit 62 is turned on in response to the signal SELb. Thus, the data signal held in a read data latch circuit 5a is given to a read data latch circuit 5b and it is outputted to an external part through the port B.