PURPOSE: To reduce the processing level of a small signal by providing the 1st∼4th parallel circuits connected especially respectively and the 1st and 2nd series circuits and not making the capacitance of the 7th capacitor zero and not making the capacitance of the 12th capacitor equal to the capacitance of the 14th capacitor so as to suppress the offset voltage lower.

CONSTITUTION: The 1st parallel circuit connected between a signal input terminal Vin and an inverting input of the 1st operational amplifier A1, the 2nd parallel circuit connected between the signal input terminal Vin and an inverting input of the 2nd operational amplifier A2, the 1st series circuit comprising a switch S15, a capacitor C12 and a switch S16, and the 2nd series circuit comprising a capacitor C1 and a switch S25 are provided. Further, the 3rd parallel circuit connected between the inverting input and an output terminal Vout of the 2nd operational amplifier A2 and the 4th parallel circuit connected between the inverting input of the 1st operational amplifier A1 and the output terminal Vout of the 2nd operational amplifier A2 are provided. Switches S1, S3, S10, S12 and S15∼S25 are driven by biphase clocks 1, 2 not overlapped together.