PURPOSE: To reduce the processing level of a small signal by providing the 1st∼4th parallel circuits connected especially respectively and the 1st and 2nd series circuits so as to suppress an offset voltage lower.
CONSTITUTION: The 1st parallel circuit connected between a signal input terminal Vin and an inverting input terminal of the 1st operational amplifier circuit A1, the 2nd parallel circuit connected between the signal input terminal Vin and an inverting input terminal of the 2nd operational amplifier A2, the 1st series circuit comprising a switch S13, a capacitor C10 and a switch S14 and the 2nd series circuit comprising a capacitor C1 and a switch S25 connected in series between the inverting input terminal and the output terminal of the 1st operational amplifier A1 are provided. Then the 3rd parallel circuit connected between the inverting input terminal and the output terminal Vout of the 2nd operational amplifier A2 and the 4th parallel circuit connected between the inverting input terminal of the 1st operational amplifier A1 and the output terminal Vout of the 2nd operational amplifier A2 are provided.