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Title:
DUAL SYSTEM FOR COMMUNICATION LINE
Document Type and Number:
Japanese Patent JPS6482720
Kind Code:
A
Abstract:

PURPOSE: To realize dual-signal-line constitution with high reliability by equipping each CPU with a port through which a fault of a communication line A is detected and a communication down signal is outputted and a control logic means which receives data from other CPUs through a communication line B.

CONSTITUTION: Each CPU 1 is equipped with the port 3 through which the fault of the communication line A is detected and the communication down signal is outputted and the control logic means 4 which receives data from other CPUs through the communication line B. Namely, each CPU 1 when detecting the fault of one communication line A(B) outputs a signal indicating that and inputs it to the control logic means 4 between the two communication lines A and B, so that data on the communication line A(B) is transferred to the other communication line B(A) through the masking of an AND. Consequently, the high-reliability dual-communication-line constitution is realized.


Inventors:
BABA TOSHIAKI
Application Number:
JP24047687A
Publication Date:
March 28, 1989
Filing Date:
September 24, 1987
Export Citation:
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Assignee:
SHIMADZU CORP
International Classes:
G05B9/02; H04L1/22; H04L13/00; H04L69/40; (IPC1-7): G05B9/02; H04L1/22; H04L13/00
Attorney, Agent or Firm:
Sadao Ikeda



 
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