Title:
DUAL SYSTEM ELECTRONIC INTERLOCKING DEVICE
Document Type and Number:
Japanese Patent JP3216996
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve processing speed and operation rate of an electronic interlocking device and to facilitate a test by arranging a starting/stopping function for data collation between two CPUs in a bus synchronous dual system configuration processing unit for performing interlocking processing in a dual system electronic interlocking device.
SOLUTION: A dual system electronic interlocking device is provided with a data collation circuit 16 by which the same processing is carried out in a first CPU 7 and a second CPU 13 on the basis of the same input information and collation between the respective data, which are the results of this processing, are carried out for determination of data correspondence between them, waiting circuit 19, 21 by which processing in the first CPU 7 and in the second CPU 13 is kept waiting and the waiting conditions of the first CPU 7 and the second CPU 13 are released when determination of data correspondence is carried out by means of a data collating means, and a reset circuit outputting reset signals to the first CPU 7 and to the second CPU 13 when data correspondence is determined.
Inventors:
Toshiro Okajima
Atsushi Mukai
Atsushi Mukai
Application Number:
JP19071896A
Publication Date:
October 09, 2001
Filing Date:
July 19, 1996
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
B61L19/06; B61L1/20; B61L21/06; G05B9/03; G06F11/16; (IPC1-7): G05B9/03; B61L19/06
Domestic Patent References:
| JP42567A |
Attorney, Agent or Firm:
Soga Doteru (6 people outside)