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Title:
DUTY ADJUSTMENT CIRCUIT
Document Type and Number:
Japanese Patent JP2008199096
Kind Code:
A
Abstract:

To provide a duty adjustment circuit capable of easily obtaining a desired duty when the duty of an input is changed.

The duty adjustment circuit is provided with: an AC coupling circuit 11 for passing an AC component of a signal S1; a bias circuit 21 including a voltage setting means having a p-MOS 23, an n-MOS 25 and a division resistor 27 and a multiplexer 33 connecting its input to the output of the division resistor 27 and outputting the voltage of a selected node 29 through an output resistor 37, and connecting the output of the multiplexer 33 to the output of the AC coupling circuit 11; and a waveform shaping circuit 41 for inputting a signal S 2 from the output of the AC coupling circuit 11 to which a DC bias component from the bias circuit 21 is added and outputting a shaped signal S3.


Inventors:
NAKAMURA YUTAKA
Application Number:
JP2007029328A
Publication Date:
August 28, 2008
Filing Date:
February 08, 2007
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H03K5/04
Domestic Patent References:
JP2003177147A2003-06-27
JPS60130918A1985-07-12
JP2001223565A2001-08-17
JP2004157770A2004-06-03
Attorney, Agent or Firm:
Hiroshi Horiguchi