To provide a dynamic frequency divider with resetting function which can be initialized in arbitrary timing.

This dynamic frequency divider when receiving a reset signal from its reset terminal sets a node 118 to a high level by a P channel MOS transistor(TR) 125, a node 119 to a low level by an N-channel MOS TR 126, a node 110 to the opposite level from a clock signal by an N-channel MOS TR 122, and a node 111 to the same level with the clock signal by a P-channel MOS TR 123. A frequency-division clock signal can therefore be risen at the rising end of the clock signal after the reset signal is inputted from the reset terminal, and the circuit can be initialized in arbitrary timing. Furthermore, since a path where a through-current flows is not formed at initialization, the power consumption does not increase at initialization.