Title:
DYNAMIC FREQUENCY DIVIDER
Document Type and Number:
Japanese Patent JP2005151284
Kind Code:
A
Abstract:
To stably obtain frequency dividing ratios 4, 8, 12, ..., 4N in a configuration of a small circuit scale and low power consumption.
Two stages of the same elements each composed of an inverter circuit 21, a capacitor 41 and a switch circuit 31 are cascade-connected. An element composed of an inverter circuit 23 and a capacitor 43 is connected to the final stage thereof. The output of the inverter circuit 23 is connected to an output terminal 2 and fed back to the input of the inverter circuit 21. The control terminals of switches 31, 32 are connected to an input terminal 1. Capacities of capacitors 41 and 43 are set to a half that of a capacitor 42.
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Inventors:
NOSAKA HIDEYUKI
KOSUGI TOSHIHIKO
TOKUMITSU MASAMI
NISHIKAWA KENJIRO
KOSUGI TOSHIHIKO
TOKUMITSU MASAMI
NISHIKAWA KENJIRO
Application Number:
JP2003387679A
Publication Date:
June 09, 2005
Filing Date:
November 18, 2003
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H03K23/66; (IPC1-7): H03K23/66
Attorney, Agent or Firm:
Tsuneaki Nagao