PURPOSE: To increase the velocity of the operation time for the circuit as a whole by precharging the data line in the reduced time over the period during which the signal inversion CE is generated and the period during which no word pulse signal is generated.

CONSTITUTION: Dynamic memory cell circuit 7 and 8 contains MISFETQM1 and QM0 which are selected by word line W1 and W0 plus capacitor C1 and C0 which function as the information selecting means, and connect precharge circuit FETQA and QB to data line D1 and D0 which connect circuit 7 and 8. FETQA and QB are controlled by chip non-selection inverse CE and the word pulse signal to give the precharge CE' to line D1 and D0 over the period of generation of signal inverse CE and the period of no generation of the word pulse signal. Thus, the precharge time is shortened, accordingly accelerating the operation time for the circuit as a whole.