PURPOSE: To speed up the memory access of a DRAM.
CONSTITUTION: This DRAM is internally provided with two row-address buffer circuits 308, 322 and a selector circuit 323 which selects either one of these circuits. A CAS signal 313 is ascertained to start CAS before RAS refreshment during the precharging period of a RAS signal in a high-speed page mode and a refreshing address 321 is latched into a buffer 308 by the ascertation of the RAS signal 305 in the next memory access. A memory address 304 from the outside is simultaneously latched into a buffer 322. A selector circuit 323 selects the buffer 308 during the refreshing period and the buffer 322 at the time of memory access to apply two pieces of the row address data taken into the two buffers to a row decoder 310 by the RAS signal 305 and the CAS signal 313, thereby ascertaining the 'row' of the memory cell array 311.
SHIOBARA TAKESHI
MASUKO ATSUSHI
ABE TAKASHI
HITACHI VIDEO & INF SYST
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