To obtain short propagation delay where overshoot and undershoot are minimum or do not exist at all by providing transmission gates controlled by the feedback of an output node between transistor control nodes of 1st and 2nd low potential sides.

1st and 2nd transmission gates 72 and 74 are connected between the gates (control nodes) of 1st and 2nd high potential side transistors 56 and 59 and also between the gates of 1st and 2nd low potential side transistors 50 and 53. In transition from high potential to low potential, the gate 72 is closed before the transition starts and it becomes low power impedance at an output node 68. When the transition of an output exceeds prescribed voltage, the gate 72 is opened and the output impedance increases. Further, when the output of an inverter 65 becomes low, a transistor 58 is turned on and a transistor 59 is turned off.