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Title:
DYNAMIC RAM INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS58111183
Kind Code:
A
Abstract:

PURPOSE: To remove coupling noises and prevent malfunction by providing the titled device with a 2-intersection cell type memory array part and connecting dummy data lines to the outsides of data lines connected to both the ends of the array part.

CONSTITUTION: A sense amplifier SA is connected to a pair of data lines DL, -DL respectively and the I/O terminals of a memory cell and a dummy cell are connected to each data line. Word lines WL and dummy word lines DWL are arranged so as to be intersected with the data lines. Dummy data lines DDL, -DDL are connected to the outside of the data lines, and these dummy data lines are provided with memory cells, dummy cells, sense amplifiers, and MOSTs for column switches so that parasitic capacity Co is made equal to that of other data lines. Thus intercomposite line capacity can be made equal in each data line in dRAM, offsetting coupling noises and preventing malfunction.


Inventors:
MATSUURA NOBUMI
Application Number:
JP20939781A
Publication Date:
July 02, 1983
Filing Date:
December 25, 1981
Export Citation:
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Assignee:
HITACHI LTD
HITACHI MICROCUMPUTER ENG
International Classes:
G11C7/02; G11C11/404; G11C11/401; G11C11/4097; G11C11/4099; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): G11C11/34; H01L27/10
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)



 
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