PURPOSE: To perform a stable operation while reducing power consumption by starting a refresh based on an output signal in which a holding voltage of a capacitor of a dummy circuit is compared with a reference voltage.
CONSTITUTION: A precharge voltage to be formed at a node N4 of a connecting point of capacitors C0 to Cn4 is input to a dummy circuit through an N-channel MOSFETQ1 to be turned ON by a timing pulse 1. The dummy circuit has a capacitor Cn1 to be substantially equivalent to a memory cell and a diffused layer Dm in which a leakage current flows. A potential of a node N1 for obtaining a holding power of the capacitor Cn1 is supplied to an input (-) of a voltage comparator CP1, and a reference voltage is supplied to an input (+) side of the comparator CP1. An output signal of the comparator CP1 is output through an AND gate, and a refresh is started based on an output signal in which an undesired output pulse is eliminated. Thus, a stable refresh can be operated while reducing power consumption.
KANEMITSU MICHITARO
AOYANAGI HIDETOMO
HITACHI VLSI ENG