Title:
DYNAMIC RANDOM ACCESS MEMORY ASSEMBLY AND ITS MODULE ASSEMBLY METHOD
Document Type and Number:
Japanese Patent JP3251887
Kind Code:
B
Abstract:
PROBLEM TO BE SOLVED: To provide a miniaturized RAM chip which is effectively used by giving an instruction so that faulty addresses are rewritten by a logic device in a response to the non-volatile memory device which stores the information on memory trouble and substituting the faulty address position of the miniaturized RAM chip for a volatile memory device.
SOLUTION: An external memory array is mapped so that the position of a faulty memory is substituted in real-time base. The main system is composed from a non-volatile memory device 14, a logic device 15, and a volatile memory device DRAM. The non-volatile memory device 14 is used to hold the address information about all troubles on a given assembly and the logic device 15 rewrites the address of the faulty RAM. The volatile memory device DRAM is used to substitute the position of the faulty address in the original miniaturized memory 131-135.
Inventors:
Timothy, Dell J.
Mark, William Kellogg
Mark, William Kellogg
Application Number:
JP1997000272312
Publication Date:
November 16, 2001
Filing Date:
October 06, 1997
Export Citation:
Assignee:
INTERNATL BUSINESS MACH CORP <IBM>
International Classes:
G11C11/401; G11C29/00; G11C29/04; (IPC1-7): G11C29/00; G11C11/401