Title:
DYNAMIC RATIOLESS CIRCUITRY FOR ADOPTING RANDOM LOGIC
Document Type and Number:
Japanese Patent JP2668611
Kind Code:
B2
Abstract:
PURPOSE: To practically remove a problem, such as the lowering of a logic level accompanied heretofore and to obtain a device having small dimensions with low power and low voltage.
CONSTITUTION: A precharge transistor 30 is connected to a voltage supply source, and this supply source is clocked by a 1st clock phase C1. A 1st node A is formed by connecting a discharge transistor 32 to the precharge transistor 30, this discharge transistor 32 is clocked by a 2nd clock phase C2 and discharging the 1st node A with a condition. The precharge transistor 30 precharges the 1st node A. an input logic device 34 forms a 2nd node B by being connected to the discharge transistor 32, and forms a discharge path from the 1st node A to a ground potential. The input logic device 34 is connected so as to receive an input signal, and an output transistor 36 generates a delayed output signal.
Inventors:
Young, Ian, A
Jean, Charles, Bee
Hildbrand, David, Bee
Jean, Charles, Bee
Hildbrand, David, Bee
Application Number:
JP8509992A
Publication Date:
October 27, 1997
Filing Date:
February 24, 1992
Export Citation:
Assignee:
Mastec, Co-Paleshan
International Classes:
H03K3/356; H03K5/08; H03K19/017; H03K5/05; H03K19/0185; H03K19/096; H03K19/20; H03K23/00; H03K23/42; H03K23/44; (IPC1-7): H03K19/096; H03K23/44
Domestic Patent References:
| JP4971860A | ||||
| JP5380355U | ||||
| JP5236828B2 | ||||
| JP5738996B2 |
Other References:
【文献】米国特許3794856(US,A)
Attorney, Agent or Firm:
Yuzo Sanada (1 person outside)
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