PURPOSE: To prevent erroneous discrimination of data by providing a sense amplifier activating timing generating circuit which can change the sense amplifier activating timing in response to a request from the outside and a circuit which causes a wait signal to be outputted against the outside in accordance with the timing generated by the generating circuit.

CONSTITUTION: A sense amplifier 1 which compares memory cell data with reference cell data is activated by a sense amplifier activating signal given from a sense amplifier activating timing generating circuit 2 through a signal line 6. When a chip activating signal is inputted to an input buffer 3, a signal which activates the sense amplifier activating timing generating circuit 2 is outputted to a signal line 4. On the other hand, when a timing changing request is inputted to the circuit 2 from an external voltage variation detect circuit through a signal line 5, the signal line 6 transmits the signal which changes the sense amplifier activating timing to the sense amplifier. When the sense amplifier activating timing is changed, a wait signal generating circuit 7 generates a wait signal against the outside. Therefore, erroneous discrimination of data can be prevented.