PURPOSE: To attain a high operating speed in excess of the speed of a conventional high speed dynamic type circuit by cross-coupling two high speed dynamic frequency dividers so as to make only one gate number included in a critical path.

CONSTITUTION: With a high level signal inputted to a reset terminal RST, transistors(TRs) N1, R1 are both turned on and a terminal MM1 reaches a high level and a terminal MM2 reaches a low level. With a clock signal inputted to a clock terminal, clocked inverters CL2, 4 are turned on, an output terminal Q reaches a low level and an output QB reaches a high level. In this case, even when the clock signal reaches a low level and the inverters CL2, 4 are turned off, when a clock frequency is at a high frequency, the frequency is kept dynamically. Since only the leakage current of a MOS TR forming the inverters CL2, 4 flows to the terminals Q, QB, the charge stored in the parasitic capacitance of the terminals Q, QB is slowly discharged and the voltage at the terminals Q, QB is kept.