Title:
【発明の名称】力率訂正回路のためのダンピングされたEMI入力フィルタ
Document Type and Number:
Japanese Patent JPH10512063
Kind Code:
A
Abstract:
An active damping circuit for an electromagnetic interference (EMI) filter for power factor correction (PFC) circuit is provided which simulates a line damping impedance which actively varies according to sensed line current. The active damping circuit comprises an nth-order, Cauer-Chebyshev, low-pass filter having input series damping impedance (Zd) simulated with a power operational amplifier and high-frequency isolation transformer. The simulated damping impedance offers greatly reduced size and power dissipation as compared to prior art passive schemes which typically require large impedance components for damping. A passive damping circuit is also shown which involves providing an alternate inductive current path in parallel with a damping resistor whereby lower frequency currents are diverted through the alternate current path and higher frequency currents continue to flow through the damping resistor. In this manner, the damping action of the damping resistor is attenuated for lower frequencies but remains unaffected for higher frequencies.
Inventors:
Latkovic, Latco
Lee, Fred Sea
Borjevic, Douzan
Lee, Fred Sea
Borjevic, Douzan
Application Number:
JP51105596A
Publication Date:
November 17, 1998
Filing Date:
September 19, 1995
Export Citation:
Assignee:
The Center for Innovative Technology
International Classes:
G05F1/70; H02M1/12; H02M1/44; H02M7/06; H03H1/00; H03H11/04; H04B15/00; (IPC1-7): G05F1/70; H04B15/00; H03H11/04; H02M7/06; H02M1/12
Attorney, Agent or Firm:
Kazuo Shamoto (5 outside)