Title:
【発明の名称】EPROMメモリセルマトリックス
Document Type and Number:
Japanese Patent JP2673529
Kind Code:
B2
Abstract:
An EPROM memory cell (C) including a source (S), a drain (D), a floating gate (F) and a control gate (G) with interposed dielectric oxide (02) is made up of two symmetrical half-cells (C1, C2) having the drain (D) and the control gate (G) in common, the sources (S) physically separated but electrically connected with each other and the floating gates (F) separated physically and electrically.
More Like This:
| WO/2013/147937 | SELECTED WORD LINE DEPENDENT SELECT GAME VOLTAGE DURING PROGRAM |
| JP2014067942 | NON VOLATILE SEMICONDUCTOR STORAGE DEVICE |
Inventors:
Giuseppe Corda
Application Number:
JP5650188A
Publication Date:
November 05, 1997
Filing Date:
March 11, 1988
Export Citation:
Assignee:
Essay essay thomson microelectronics sochieta peranonima
International Classes:
G11C16/04; G11C16/06; H01L21/8246; H01L21/8247; G11C17/00; H01L27/10; H01L27/112; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP6224675A | ||||
| JP5961189A |
Attorney, Agent or Firm:
Shinichi Ogawa (2 outside)