Title:
MANUFACTURE FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3201374
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a manufacture for a semiconductor device which reduces source parasitic resistance, without increasing the number of steps and has a low resistance gate electrode.
SOLUTION: In a manufacture for a semiconductor device having a gate electrode 1, and an ohmic electrode 3 which comes into ohmic contact with an active layer, a source electrode lead-out wiring 2 disposed at the side of a drain lead-out pad rather than the active layer is formed at the same time as the gate electrode 1. At the same time, when the ohmic electrode 3 is formed, an ohmic metal 9 is deposited on a region of the source electrode lead-out wiring 2. Further more, when a wring 4 is formed, a plating is grown in order to also form the wiring 4 selectively on the region of the source electrode lead- out wiring 2 not which does intersect the wiring 4.
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Inventors:
Yasutoshi Tsukada
Application Number:
JP4112399A
Publication Date:
August 20, 2001
Filing Date:
February 19, 1999
Export Citation:
Assignee:
NEC
International Classes:
H01L21/338; H01L21/28; H01L29/417; H01L29/812; (IPC1-7): H01L21/338; H01L21/28; H01L29/417; H01L29/812
Domestic Patent References:
| JP3265146A | ||||
| JP8153881A | ||||
| JP496339A | ||||
| JP56131965A | ||||
| JP62181475A | ||||
| JP418736A | ||||
| JP5481087A |
Attorney, Agent or Firm:
Naka Kanno