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Title:
ECHO CANCELER
Document Type and Number:
Japanese Patent JPS5713828
Kind Code:
A
Abstract:

PURPOSE: To achieve echo cancellation by an LSI chip united with an encoder and decoder by generating a pseudo-echo signal through the function of multiplication type D/A conversion built in the encoder and decoder by inputting a nonlinear PCM signal consisting of a small number of bits.

CONSTITUTION: A D/A converter 22 built in a decoder 20 is used as the multiplication type D/A converter of a pseudo-echo signal generator 30. This converter 22 is used in time-division mode for PCM signal decoding operation and echo-canceling operation in every sampling period. In the PCM signal decoding operation, the converter 22 is applied with a reference voltage Vref as a reference voltage and this voltage Vref and an input PCM signal X'j are multiplied by each other to obtain an analog signal Xj. In the echo-canceling operation, the converter 22 is supplied with coefficients hji one after another and those coefficients and PCM signal Xj-j inputted from a delay circuit one after another are multiplied by each other. Then, the output of the converter 22 is led via a switch to an integrator, from which an echo- canceled signal is obtained.


Inventors:
AMADA EIICHI
SUZUKI TOSHIROU
KOSUGI HIROSHI
Application Number:
JP8662180A
Publication Date:
January 23, 1982
Filing Date:
June 27, 1980
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H04B3/23; (IPC1-7): H04B3/23



 
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