EDC LSI CHECKING DEVICE

Title:

EDC LSI CHECKING DEVICE

Document Type and Number:

Japanese Patent JPH0652008

Kind Code:

A

Abstract:

PURPOSE: To confirm an normal operation of a general purpose EDC LSI by a simple hardware constitution.

CONSTITUTION: An EDC bit inversion control part 9 transmits alternately an output enable signal to a data 1-bit, inverting part 15 and a data 2-bit inverting part 16 so that data subjected to 1-bit 2-bit inversion is sent to an EDC LSI 3, and a central control processor 17 executes a read-out operation to a main storage device 1. The main storage device 1 transmits the data subjected to 1-bit or 2-bit inversion to the EDC LSI 3 by the data 1-bit inverting part 15 or the data 2-bit inverting part 16. The EDC LSI 13 transmits 1-bit, 2-bit error report signals 6, 7 to a register 8, when a bit error detecting circuit 4 receives the data subjected to 1-bit, 2-bit inversion, and the register 8 confirms a fact that a 1-bit, 2-bit error detecting circuit is operating normally.

Inventors:

BABA YUJI

Application Number:

JP20638292A

Publication Date:

February 25, 1994

Filing Date:

August 03, 1992

Export Citation:

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Assignee:

NEC CORP

International Classes:

G06F11/22; (IPC1-7): G06F11/22

Attorney, Agent or Firm:

Naoki Kyomoto (2 outside)

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