Title:
電力および面積面で効率良い適応等化処理
Document Type and Number:
Japanese Patent JP4668988
Kind Code:
B2
Abstract:
Methods, apparatuses, and systems are presented for performing channel equalization comprising receiving a signal from a channel associated with inter-symbol interference, processing the received signal to effectively apply a plurality of linearly independent impulse responses to the received signal to produce a plurality of intermediate signals, scaling each of the intermediate signals by each of a plurality of multiplier factors to produce a plurality of scaled signals, and combining the scaled signals to produce a resulting signal corresponding to an equalized version of the received signal in order to reduce effects of inter-symbol interference. Processing of the received signal may comprise providing the received signal to an LCR network comprising a plurality of inductors and a plurality of capacitors and generating, as the intermediate signals, a plurality of inductor signals representing currents through the plurality of inductors and a plurality of capacitor signals representing voltages across the plurality of capacitors.
Inventors:
Pavan, shanti
Application Number:
JP2007516597A
Publication Date:
April 13, 2011
Filing Date:
June 09, 2005
Export Citation:
Assignee:
VITESSE SEMICONDUCTOR CORPORATION
International Classes:
H04B3/06; H03B1/00; H03K5/00; H04B1/10; H04L25/03
Domestic Patent References:
| JP2000224080A | ||||
| JP11196046A | ||||
| JP9500776A | ||||
| JP4233313A | ||||
| JP6350328A | ||||
| JP2002280960A |
Attorney, Agent or Firm:
Atsushi Aoki
Jun Tsuruta
Tetsuro Shimada
Kurachi Yasuyuki
Shimichi Akihisa
Jun Tsuruta
Tetsuro Shimada
Kurachi Yasuyuki
Shimichi Akihisa
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