Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ELAPSED TIME COUNTER
Document Type and Number:
Japanese Patent JPS5547478
Kind Code:
A
Abstract:

PURPOSE: To eliminate timer enable flip-flop in an elapsed time counter provided in a computer or the like by detecting that the content of a timer register becomes negative to thereby automatically stop the counting operation.

CONSTITUTION: A timer register 11 set in advance with positive value subtracts the output of a circuit 14 for detecting that the content of the timer register is negative maximum value by the output form an oscillator 13 to detect that the content becomes zero by a detector 15 so as to produce a timer interrupt request signal 16. The timer register continues subtraction while the signal 16 is queued, and when the difference becomes negative maximum value, the output of the circuit 14 becomes zero to thereby close an AND gate 12. When positive value is set in the register 11, the elapsed time counter again starts operation.


Inventors:
SATOU FUMITAKA
MURAYAMA MASAKI
Application Number:
JP12074978A
Publication Date:
April 03, 1980
Filing Date:
September 30, 1978
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G04F1/00; G04F10/00; G04G99/00; (IPC1-7): G04F10/04; G04G1/00