PURPOSE: To realize the high-speed performance together with the large capacity and to minimize throughput by switching a high-speed elastic store circuit having the large throughput and the large capacity and another elastic store circuit having the minimum throughput and the small capacity in accordance with the phase difference between the write and read resetting signals.

CONSTITUTION: An elastic store circuit 1 using two faces of memory cells has the large throughput despite its small capacity and high-speed performance. While an elastic store circuit 2 using a flip-flop train has the small capacity despite its small throughput and high-speed performance. Then a selector 4 is switched according to the phase difference between the write and read resetting signals showing the breaks of data. Thus the output data is obtained. In such a way, an elastic store circuit is obtained with the small throughput, the large capacity and the high speed performance respectively.