To detect an output data omission, which cannot be recognized by parity check, by internally providing a detecting means for the output data omission.

This detecting means for the output data omission is provided in the inside. In this case, it is decided whether the numbers of write and read clocks within a specified cycle match by the output of an exclusive OR element 10 for inputting a final write address count-up value 5 (WAXE), immediately before being initialized by a write address counter reset pulse (WRP) and a final read address count-up value 9 (RACE) immediately before initialized by a read address counter reset pulse, (RRP) and the state of non-matching is stored in a flip-flop(FF) 27 of the poststage. Then, the output of a write/read time non-matching detecting signal (OD-CHK) is continued to the outside of the elastic store memory, until inputting a signal (ERRCLR) for clearing the state from counter communication equipment.