PURPOSE: To provide an electric field effect transistor capable of suppressing a leakage current and reducing current consumption.

CONSTITUTION: Input signals VIN outputted from an internal logic circuit 17 are inputted to a NAND circuit 13 as the input signals IN1 and inputted to a NOR circuit 14 as the input signals IN3 as they are and delayed by an inverter group 15 for delay and inputted to the NAND circuit 13 and the NOR circuit 14 as the input signals IN2. Thus, a timing when the output signals S1 of the NAND circuit 13 and the output signals S2 of the NOR circuit 14 are switched to high (Hi) and low (Low) is shifted by delay time and the timing when a PMOS11 and an NMOS12 are turned on/off is shifted. As a result, a period when the PMOS11 and the NMOS12 are both turned off is provided, the leakage current is suppressed and power consumption is reduced.