Title:
ELECTRICALLY PROGRAMMABLE AND ERASABLE MEMORY CELL
Document Type and Number:
Japanese Patent JPS58115865
Kind Code:
A
Abstract:
An electrically programmable and eraseable memory cell in which charge carriers are tunnelled between a floating gate and a drain region in the substrate through a thin oxide tunnel region, the borders of said tunnel region being confined to a small area well inside the borders of both the drain region and the floating gate. Dual paths are utilized to connect the tunnel region of the gate to the memory cell region of the gate.
Inventors:
JIORA YARON
IN KUEN SUN
URAI PURIIRU
JIYAYASHIMUHA ESU PURASADO
MAAKU ESU EBURU
IN KUEN SUN
URAI PURIIRU
JIYAYASHIMUHA ESU PURASADO
MAAKU ESU EBURU
Application Number:
JP19669682A
Publication Date:
July 09, 1983
Filing Date:
November 09, 1982
Export Citation:
Assignee:
NAT SEMICONDUCTOR CORP
International Classes:
H01L21/8247; H01L21/8246; H01L27/112; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): G11C17/00; H01L27/10; H01L29/78
Domestic Patent References:
| JPS55105374A | 1980-08-12 |
Attorney, Agent or Firm:
Kyozo Yuasa