Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ELECTRONIC CIRCUIT DEVICE AND PACKAGING BOARD
Document Type and Number:
Japanese Patent JP2001135773
Kind Code:
A
Abstract:

To provide an electronic circuit device which can suppress parasitic inductance by mounting a high-frequency device or the like on a packaging board and be provided with a capacitor element the area, of which can be reduced the packaging board for mounting a high-frequency device and the like.

This electronic circuit device has a semiconductor device having a semiconductor chip 10, on which an electric circuit is formed and at least one planar electrode 11b formed on the semiconductor chip, to be connected to the electronic circuit, a substrate S, a packaging board electrode 24b formed on the substrate surface and a capacity insulating film 25a formed on the packaging board electrode 24b. The semiconductor device is mounted on the packaging board, so that the planar electrode 11b is disposed on the packaging board electrode 24b via the capacitance insulating film 25a to form a capacitor element Cap.


Inventors:
HIRABAYASHI TAKAYUKI
Application Number:
JP31872799A
Publication Date:
May 18, 2001
Filing Date:
November 09, 1999
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SONY CORP
International Classes:
H01L23/12; H01L25/00; (IPC1-7): H01L25/00; H01L23/12
Attorney, Agent or Firm:
Takahisa Sato